The present disclosure is related to an opto-electrical integration, more particularly, to a compact optical transceiver based on Die-on-Package multichip stacking integration utilizing low cost Fan-Out Wafer Level Packaging (FOWLP) architecture and through-mold via (TMV) technology.
As science and technology are updated rapidly, processing speed and capacity of the computer increase correspondingly. The communication transmission or reception using the traditional cable is limited to bandwidth and transmission speed of the traditional cable and mass information transmission required in modern life causes the traditional communication transmission overload. To correspond to such requirement, the optical fiber transmission system replaces the traditional communication transmission system gradually. The optical fiber communication is chosen for systems requiring higher bandwidth and longer distance that electrical cable cannot accommodate. Present electronic industrial performs research toward optical transmission which will become the mainstream in the future even for short distance communication. Said optical communication is a technology in that light wave functions as signal carrier and transmitted between two nodes via the optical fiber. An optical communication system includes an optical transmitter and an optical receiver. By the optical transceiver, the received optical signal can be converted to an electrical signal capable of being processed by an IC, or the processed electrical signal can be converted to the optical signal to be transmitted via optical fiber. Therefore, objective of communication can be achieved.
With the advances of optical communication technology and applications driven by the market, the demands become stronger on increasing bandwidth for optical communication and decreasing package footprint of an optical transceiver. It is more and more challenging to integrate all necessary components within smaller and smaller module package. For the state-of-art optical transceiver products, all the critical components including clock data recovery (CDRs), modulator drivers, transimpedance amplifiers (TIAs), and photonics chips having optical passives, modulators, and photo detectors, are assembled side-by-side on a PCB in a 2D fashion. This approach has at least two drawbacks for developing any future optical transceiver with data rate greater than 400 G. Firstly, the side-by-side placement of the components consumes much of the board area for optical transceiver as a pluggable product or major substrate area for on-board optics product, making it very difficult to further shrink the product size. Secondly, side-by-side placement on the PCB creates longer electrical transmission length and often requires wire bonds between electrical die and photonics die, introducing more electrical loss which damages signal integrity for very high data rate transceiver product, e.g., >56 Gbaud symbol rate. In particular, the wire bonds lead to impedance mismatch due to large inductance, degrading the signal a lot at higher frequencies. As such, it is not practical to use wirebond as electrical interconnect between chips or between chips and board for the applications where high frequency (e.g., >40 GHz) analog signal is transmitted. The large inductance of wire bonds has become a bottle neck of high speed signal transmission.
To shorten the interconnect length of conventional wire bonds between electronics devices (e.g., from LD driver/TIA to digital signal processor DSP) or between electronics (driver/TIA) and photonics (e.g., CDR and PAM4 ASIC), people have started to use through-silicon via (TSV) process in Si photonics die to replace wire bonds and make interconnections. However, TSV process is still ready for mass production due to high cost of performing the process and handling thin wafer. Moreover, the current infrastructure and investment only allow for fine TSV process in 12-inch wafers. This limits the flexibility of TSV-based interconnects to be employed in various technologies that use substrate size less than 12-inch, e.g., 8-inch SiGe process, 8-inch BiCMOS process, GaAs-substrate process, InP-substrate process, and 8-inch MEMS process. The complexity of manufacturing process, low yield, inefficient wafer area usage, and very expensive in scaling to advanced electronics making the TSV process impractical for making Si photonics field product. Therefore, there is demand on alternative solutions for integrating electronics functions and photonics circuits to meet the requirement of ever increasing bandwidth between electronics and photonics. It is desired to have an improved packaging scheme that enjoys the high performance benefit of a 3D multichip stacking integration with much shorter interconnect and lower parasitic while keeping the packaging process simple and cost low.